The phase-noise performance of a voltage controlled oscillator (VCO) affects different specifications of analog circuits, such as the error-vector-magnitude (EVM) or the signal-to-noise ratio (SNR). One major source of noise for VCOs comes from the VCO's voltage supply. Supply noise has been shown to have a substantial impact on VCO phase noise in terms of deterministic noise. Any signal or noise on voltage supply lines will progress to the active circuitry through stray capacitances and gain of the bias network and be amplified by active circuitry of a system on a chip (SoC). These unwanted noise signals degrade device performance.
If the voltage supply of an operational amplifier (op-amp) changes, the voltage output of the op-amp should not—yet, it typically does. If a change of X volts in the op-amp's supply produces an output voltage change of Y volts, the dimensionless ratio of supply voltage to output voltage (i.e., X/Y) is commonly referred to as power supply rejection ratio (PSRR) on that supply, or simply power supply rejection (PSR) if expressed in decibels (dBs). PSRR is a measure of how well a circuit rejects supply noise, or “ripple,” coming from an input power supply at various frequencies, and is very critical in many radio frequency (RF) circuits.
An open-loop PSRR curve is predominately shaped by a phase lock loop (PLL) transfer function, and the supply dependent noise at the output of the VCO is typically high-pass filtered. The PLL loop itself acts like a high pass filter for the noise at the VCO, attenuating the low frequency noise to the bandwidth of the PLL. Jitter due to the supply noise outside the bandwidth of the PLL is directly seen at the output, and thus subsequently passed to the other circuitry of the SoC.